1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device allowing reduction of I/O terminals in a slow operation mode.
2. Description of the Background Art
A DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is now available as a semiconductor memory device, which has a large capacity and can perform fast input/output of data.
Referring to FIG. 33, a DDR-SDRAM 200 includes an address buffer 210, a clock buffer 220, a control signal buffer 230, a control circuit 240, a mode register 250, a memory cell array 260, a DLL (Delay Locked Loop) 270, an I/O buffer 280, a QS buffer 290 and data buses BS1 and BS2.
Address buffer 210 externally receives addresses A0-A12 and bank addresses BA0 and BA1, and buffers received addresses A0-A12 and bank addresses BA0 and BA1. Address buffer 210 provides buffered addresses A0-A12 and bank addresses BA0 and BA1 to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220.
Clock buffer 220 externally receives clocks CLK and /CLK as well as a clock enable signal CKE, and buffers received clocks CLK and /CLK as well as received clock enable signal CKE with an internal reference voltage INTVREF. Reference voltage INTVREF has the same voltage as an externally received reference voltage VREF. Clock buffer 220 provides buffered clocks BUFF_CLK and BUFF_/CLK to control signal buffer 230, control circuit 240 and DLL 270, and provides buffered clock enable signal CKE to control circuit 240.
Control signal buffer 230 externally receives a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM, and buffers the received control signals such as chip select signal /CS with reference voltage INTVREF. Control signal buffer 230 provides the buffered control signals such as chip select signal /CS to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220.
Control circuit 240 determines the next rising of clocks BUFF_CLK and BUFF_/CLK as valid if clock enable signal CKE was at an H (logical high) level at the time of rising of clocks BUFF_CLK and BUFF_/CLK received from clock buffer 220. If clock enable signal CKE was at an L (logical low) level at the time of rising of clocks BUFF_CLK and BUFF_/CLK, control circuit 240 determines the next rising of clocks BUFF_CLK and BUFF_/CLK as invalid.
When clocks BUFF_CLK and BUFF_/CLK are determined as valid, control circuit 240 controls semiconductor memory device 200 based on chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE and data mask signal DM received from control signal buffer 230.
More specifically, control circuit 240 recognizes the selection of semiconductor memory device 200 based on chip select signal ICS at L-level, and recognizes the nonselection of semiconductor memory device 200 based on chip select signal /CS at H-level. Control circuit 240 selects one of all of a plurality of banks included in memory cell array 260 based on bank addresses BA0 and BA1 sent from address buffer 210. Further, control circuit 240 determines addresses A0-A12, which are received from address buffer 210 in accordance with the timing of switching of row address strobe signal /RAS from H-level to L-level, as a row address, and provides the row address to memory cell array 260 in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220.
Further, control circuit 240 determines addresses A0-A12, which are received from address buffer 210 in accordance with the timing of switching of column address strobe signal /CAS from H-level to L-level, as a column address, and provides the column address to memory cell array 260 in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220.
Control circuit 240 recognizes the data write mode or data read mode based on write enable signal /WE. In the write mode, control circuit 240 controls I/O buffer 280 such that write data sent from I/O terminals DQ0-DQ7 may be provided to memory cell array 260 in synchronization with an internal data strobe signal INTDQS sent from QS buffer 290, and also controls QS buffer 290 such that internal data strobe signal INTDQS prepared by buffering an externally supplied data strobe signal DQS is provided to I/O buffer 280. In the read mode, control circuit 240 controls I/O buffer 280 such that the data read from memory cell array 260 via data bus BS2 is provided to I/O terminals DQ0-DQ7 in synchronization with period signal DLLCLK_P or DLLCLK_N sent from DLL 270, and also controls QS buffer 290 such that period signal DLLCLK_P or DLLCLK_N sent from DLL 270 is provided to an I/O terminal DQS.
Control circuit 240 controls I/O buffer 280 based on data mask signal DM. More specifically, control circuit 240 operates in the write mode to control I/O buffer 280 based on data mask signal DM at H-level such that the write data may not be written into memory cell array 260 while data mask signal DM is at H-level, and to control I/O buffer 280 based on data mask signal DM at L-level such that all the write data may be written into memory cell array 260. Further, control circuit 240 operates in the read mode to deactivate I/O buffer 280 based on data mask signal DM at H-level and to activate I/O buffer 280 based on data mask signal DM at L-level.
Further, control circuit 240 controls the timing for actually reading the data after instruction of the data read operation based on a CAS latency set by mode register 250, and activates or deactivates DLL 270 in accordance with the instruction sent from mode register 250.
Mode register 250 sets a CAS latency CL and provides it to control circuit 240. Mode register 250 instructs control circuit 240 to activate or deactivate DLL 270.
Memory cell array 260 includes the plurality of banks, and stores the data.
DLL 270 produces period signals DLLCLK_P and DLLCLK_N based on clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220, and provides these period signals DLLCLK_P and DLLCLK_N to I/O buffer 280 and QS buffer 290.
In the write mode, I/O buffer 280 writes the write data sent from I/O terminals DQ0-DQ7 into memory cell array 260 in synchronization with internal data strobe signal INTDQS sent from QS buffer 290. In the read mode, I/O buffer 280 provides the read data read from memory cell array 260 via data bus BS2 to I/O terminals DQ0-DQ7 in synchronization with period signals DLLCLK_P and DLLCLK_N sent from DLL 270.
In the write mode, QS buffer 290 buffers externally supplied data strobe signal DQS, and provides buffered internal data strobe signal INTDQS to I/O buffer 280. In the read mode, QS buffer 290 provides period signals DLLCLK_P and DLLCLK_N received from DLL 270 to I/O terminal DQS.
Data bus BS1 provides the control signals such as addresses A0-A12 and row address strobe signal /RAS, which are sent from control circuit 240, to memory cell array 260. Data bus BS2 transmits the write data and read data between memory cell array 260 and I/O buffer 280.
Referring to FIG. 34, description will now be given on the operation of writing data into memory cell array 260 in DDR-SDRAM 200. It is assumed that DDR-SDRAM 200 is externally supplied with reference voltage VREF, and clock buffer 220, control signal buffer 230 and QS buffer 290 receive internal reference voltage INTVREF having the same voltage level as reference voltage VREF.
When the write operation starts, clocks CLK and /CLK as well as clock enable signal CKE are externally supplied to DDR-SDRAM 200. Clock buffer 220 buffers clocks CLK and /CLK, and provides buffered clocks BUFF_CLK and BUFF_/CLK to address buffer 210, control signal buffer 230, control circuit 240 and DLL 270. Clock buffer 220 buffers clock enable signal CKE, and provides buffered clock enable signal CKE to control circuit 240.
DDR-SDRAM 200 is also externally supplied with chip select signal /CS at L-level. Control signal buffer 230 buffers chip select signal /CS at L-level with internal reference voltage INTVREF, and provides buffered chip select signal /CS at L-level to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
Control circuit 240 determines at certain rising of clock BUFF_CLK or BUFF_/CLK whether clock enable signal CKE is at H-level or L-level. When clock enable signal CKE is at H-level, control circuit 240 will determine chip select signal /CS at L-level as valid in response to the next rising of clock BUFF_CLK or BUFF_/CLK, and sets DDR-SDRAM 200 to the selected state.
Thereafter, DDR-SDRAM 200 is externally supplied with write enable signal /WE at L-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level, and control signal buffer 230 buffers write enable signal /WE at L-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level with internal reference voltage INTVREF. Control signal buffer 230 provides write enable signal /WE at L-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level thus buffered to control circuit 240.
Control circuit 240 recognizes the data write mode in accordance with write enable signal /WE at L-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level sent from control signal buffer 230.
In the write mode, mode register 250 instructs control circuit 240 to deactivate the output of DLL 270, and control circuit 240 deactivates the output of DLL 270 in accordance with the instruction of mode register 250.
Thereafter, DDR-SDRAM 200 is externally supplied with bank addresses BA0 and BA1. Address buffer 210 buffers bank addresses BA0 and BA1, and provides buffered bank addresses BA0 and BA1 to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
Control circuit 240 selects one bank from the plurality of banks included in memory cell array 260 based on bank addresses BA0 and BA1 sent from address buffer 210.
DDR-SDRAM 200 is externally supplied with addresses A0-A12. Address buffer 210 buffers addresses A0-A12, and provides buffered addresses A0-A12 to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK. Row address strobe signal /RAS at L-level is externally supplied to DDR-SDRAM 200, and control signal buffer 230 operates in the manner already described to buffer row address strobe signal /RAS at L-level and to provide buffered row address strobe signal /RAS at L-level to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
Control circuit 240 determines or regards addresses A0-A12 received from address buffer 210 as a row address in accordance with row address strobe signal /RAS at L-level, and provides the row address to memory cell array 260 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
DDR-SDRAM 200 is externally supplied with column address strobe signal /CAS at L-level, and control signal buffer 230 buffers column address strobe signal /CAS at L-level with internal reference voltage INTVREF, and provides buffered column address strobe signal /CAS at L-level to control circuit 240 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
Control circuit 240 determines or regards addresses A0-A12 sent from address buffer 210 as a column address in accordance with column address strobe signal /CAS at L-level, and provides the column address to memory cell array 260 in synchronization with clocks BUFF_CLK and BUFF_/CLK.
QS buffer 290 receives data strobe signal DQS from I/O terminal DQS, and buffers received data strobe signal DQS with internal reference voltage INTVREF. QS buffer 290 provides buffered internal data strobe signal INTDQS to I/O buffer 280.
I/O buffer 280 provides write data DQW received from I/O terminals DQ0-DQ7 in synchronization with the rising and falling of data strobe signal DQS, and buffers write data DQW thus received. I/O buffer 280 provides buffered write data DQW to memory cell array 260 in synchronization with the rising and falling of internal data strobe signal INTDQS sent from QS buffer 290.
In memory cell array 260, a row decoder (not shown) decodes the row address sent from control circuit 240, and activates the word line designated by the decoded row address. A column decoder (not shown) decodes the column address sent from control circuit 240, and activates a bit line pair designated by the decoded column address. Write data DQW is written into a memory cell designated by the active word line and the active bit line pair.
In DDR-SDRAM 200, as described above, write data DQW is supplied to DDR-SDRAM 200 in synchronization with the rising and falling of data strobe signal DQS, and is written into the memory cell in synchronization with the rising and falling of internal data strobe signal INTDQS.
Referring to FIG. 35, description will now be given on the operation of reading data from the memory cell in DDR-SDRAM 200. In the read operation, it is assumed that DDR-SDRAM 200 is externally supplied with reference voltage VREF, and clock buffer 220, control signal buffer 230 and QS buffer 290 are supplied with internal reference voltage INTVREF having the same voltage level as reference voltage VREF.
When the read operation starts, DDR-SDRAM 200 is externally supplied with clocks BUFF_CLK and BUFF_/CLK, clock enable signal CKE and chip select signal /CS at L-level. After the above start, the operations are performed in the same manner as those for the data writing until control circuit 240 sets DDR-SDRAM to the selected state.
When DDR-SDRAM 200 enters the selected state, DDR-SDRAM 200 is externally supplied with write enable signal /WE at H-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level, and control signal buffer 230 buffers write enable signal /WE at H-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level with internal reference voltage INTVREF. Control signal buffer 230 provides buffered write enable signal /WE at H-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level to control circuit 240.
Thereby, control circuit 240 recognizes the data read mode in accordance with write enable signal /WE at H-level, row address strobe signal /RAS at H-level and column address strobe signal /CAS at L-level sent from control signal buffer 230.
In the read mode, mode register 250 instructs control circuit 240 to activate the output of DLL 270, and control circuit 240 activates the output of DLL 270 in accordance with the instruction sent from mode register 250. Mode register 250 sets CAS latency CL, and control circuit 240 controls I/O buffer 280 to provide externally the read data in accordance with CAS latency CL designated by mode register 250.
DLL 270 produces period signals DLLCLK_P and DLLCLK_N, which have predetermined phases with respect to clocks CLK and /CLK, based on clocks BUFF_CLK and BUFF_/CLK sent from clock buffer 220, and provides period signals DLLCLK_P and DLLCLK_N thus produced to I/O buffer 280 and QS buffer 290.
DDR-SDRAM 200 is externally supplied with bank addresses BA0 and BA1, and the bank is designated by bank addresses BA0 and BA1 in the same manner as the write operation.
DDR-SDRAM 200 is externally supplied with addresses A0-A12. Operations are performed in the same manner as those for the data writing so that the row and column addresses are supplied to memory cell array 260, and the memory cell activated by the row and column addresses is activated.
Data is read from the memory cell thus activated, and a sense amplifier (not shown) included in memory cell array 260 amplifies and provides read data DQR to I/O buffer 280 via data bus BS2.
Thereby, in accordance with timing determined by CAS latency CL (CAL=2.5 in the example illustrated in FIG. 35), which is set by mode register 250, I/O buffer 280 provides read data DQR to I/O terminals DQ0-DQ7 in synchronization with the rising of period signals DLLCLK_P and DLLCLK_N sent from DLL 270. QS buffer 290 provides period signals DLLCLK_P and DLLCLK_N received from DLL 270 to I/O terminal DQS.
In DDR-SDRAM 200, as described above, data is read from the memory cell in synchronization with clocks BUFF_CLK and BUFF_/CLK, and read data DQR is externally sent in synchronization with period signals DLLCLK_P and DLLCLK_N produced inside DDR-SDRAM 200.
However, the conventional DDR-SDRAM employs clock /CLK complementary to clock CLK as well as externally supplied reference voltage VREF and data strobe signal DQS for ensuring a fast operation margin. Therefore, in slow tester evaluation, a production test and a slow system, which do not require a fast operation margin, such a problem arises that the SDRAM has more pins that a usual SDRAM, and the number of DDR-SDRAMs, which can be tested simultaneously, is reduced.
Accordingly, an object of the invention is to provide a semiconductor memory device, which allows reduction of external pins in a slow operation mode.
According to the invention, a semiconductor memory device for operating either in a normal operation mode for periodically performing writing and reading of data or in a slow operation mode for periodically performing writing and reading of the data at a lower speed than that in the normal operation mode, includes a plurality of memory cells, a signal select circuit and a peripheral circuit.
The plurality of memory cells store the data. The signal select circuit selects either a first signal received from an I/O terminal used only in the normal operation mode or a second signal received from an I/O terminal used in both the slow and normal operation modes. The peripheral circuit performs the writing and/or reading of the data into and/or from the plurality of memory cells in the slow operation mode by using the second signal selected when the signal select circuit selects the second signal, and performs the writing and/or reading of the data into and/or from the plurality of memory cells in the normal operation mode by using the first signal when the signal select circuit selects the first signal. The signal select circuit selects the first signal in the normal operation mode, and selects the second signal in the slow operation mode.
According to the invention, therefore, the number of I/O terminals used in the slow operation mode can be smaller than that of I/O terminals used in the normal operation mode.
Consequently, it is possible in the slow tester evaluation, production test and slow system to increase the number of semiconductor memory devices, which can be tested simultaneously. Further, a user using the semiconductor memory device in the slow operation mode can reduce a cost.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.